The present invention relates generally to the design of cache memories in computer central processor units (CPU""s), and particularly to the detection and resolution of coherence protocol races within a chip multiprocessor node (i.e., a chip with multiple CPU""s).
In chip multiprocessor systems, it is advantageous to split the coherence protocol into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is typically implemented by the second-level cache controller (xe2x80x9ccache controllerxe2x80x9d). The other protocol is responsible for cache coherence management across chip multiprocessor nodes (xe2x80x9cnodesxe2x80x9d), and is typically implemented by separate cache coherence protocol engines (xe2x80x9cprotocol enginesxe2x80x9d). The cache controller and the protocol engine need to communicate and synchronize memory transactions involving multiple nodes. In particular, there must be a single serialization point within each node that resolves races within the node. Specifically, the serialization point must address situations in which the protocol engine and the cache controller overlap in their respective processing of memory transactions concerning the same memory line of information.
This invention relates to the design of cache coherence protocol for a scalable shared memory system composed of chip multiprocessor nodes, that is, each processor chip contains multiple CPUs, each CPU with its own private instruction and data caches (first-level caches) and all CPUs sharing a single second-level cache. Cache coherence is maintained among all caches within a chip, as well among all caches across the nodes by a protocol engine and a cache controller that are included in each node of the system. The protocol engine and the cache controller often interact to complete each of these tasks. If messages exchanged between the protocol engine and the cache controller concerning a particular cache line overlap, the protocol engine requests additional processing instructions from the cache controller and stall action on the message received from the cache controller until after receiving the additional processing instructions from the cache controller. The protocol engine is further configured to stall action on messages concerning the same cache line and received from other nodes until after receiving the processing instructions from the cache controller.